Only the value of D at the positive edge matters. Positive edge triggering When the output responds to the change in the input only at the positive edge of the clock pulse, then the clock pulse is said to be a positive edge triggered. However, a flip-flop will be used as part of the circuits in chapter 10. Edge-triggered: Read input only on edge of clock cycle (positive or negative) Example below: Positive Edge-Triggered D Flip-Flop On the positive edge (while the clock is going from 0 to 1), the input D is read, and almost immediately propagated to the output Q. In edge triggering, the flip flop changes its state during the positive edge or negative edge of the clock pulse. So this chapter will not implement a flip-flop. circuit is called an edge-triggered D-type flip-flop, as the value on the D input of FF1 (the circuit’s data input) is stored in the circuit, and output on the Q of FF2, on the 01 transition of Clock. A positive and a negative edge- triggered flip-flop both sample the D input, and the appropriate flip-flop is selected for the output. A clock pulse used to operate a flip flop is illustrated in Figure 1 (a). Unlike single-edge triggered flip-flops, they capture data on both edges of a clock. This is illustrated in Figure \(\PageIndex\): Actual implementation of a D flip-flopĭue to a problem known as debouncing, it is hard to illustrate a flip-flop in isolation as a circuit. 2.3 Single Edge Triggered and Double Edge Triggered Flip Flops In some systems double-edge-triggered flip-flops are required. The master takes the flip-flops inputs: D (data) and C (clock). This flip-flop is built from two gated latches: one a master D latch, and the other a slave SR latch. The concept behind a flip-flop is that current flowing within a circuit is not instantaneous, but always has a short delay depending on the size of the circuit, the gates that it must traverse, etc. The D flip-flop described here is positive edge-triggered which means that the input which is stored is that input which is seen when the input clock transitions from 0 to 1. All flip-flops in this text will be positive edge trigger. The flip-flop can be triggered by a raising edge (0->1, or positive edge trigger) or falling edge (1->0, or negative edge trigger). It is said to trigger on the edge of the clock pulse, and thus is called an edge-triggered flip-flop. An edge triggered flip-flop (or just flip-flop in this text) is a modification to the latch which allows the state to only change during a small period of time when the clock pulse is changing from 0 to 1.
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